Accomplishments

Design of a Timing Signal Generator (TSG) for RADAR using FPGA


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Category
Conference
Conference Name
Second International Conference Emerging Trends in Engineering and Technology,
Conference From
17-Dec-2009
Conference To
19-Dec-2009
Conference Venue
Raisoni College of Engineering Nagpur
  • Abstract

The paper discusses the application of VLSI technology to implement the functions of TSG of a radar system using VHDL with behavioral model, as the HDL and targeting it to a FPGA. The TSG is the heart of radar application to generate timing and control signals to operate radar in different phases like detection, tracking and acquisition, and hold mode. The advantage of TSG design with FPGA is that TSG unit assembly gets mounted into a single chip, parallel processing is done and changes at the hardware are possible through programming from remote without consumption of time and money.

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