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Model-Based Design of LTE Base Band Processor Using Xilinx System Generator in FPGA


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Category
Articles
Publisher
Arpn Publishers
Publishing Date
01-Aug-2015
volume
10
Issue
14
Pages
5941–5946
  • Abstract

Long Term Evolution (LTE) is likewise brought up to as Evolved - Universal Terrestrial Radio Access (EUTRA). The specifications define a new physical air interface in order to increase of the data rate of the cellular mobile wireless. In this paper, to appraise the effectiveness of LTE physical layer, the Reed-Solomon coder is used for Forward Error Correction (FEC) in systems where the data are transferred and vulnerable to errors before the reception. In an indispensable of convolution encoder, based on the encoder output rate more than to 2 bits are sent over the channel for every input bit. It is employed in a full combination of error correcting applications and frequently used in terminal with the Viterbi Decoder. These subsystems are implemented in MATLAB/Simulink model based design and the analysis of power parameter like Total power, Thermal power, Quiescent, Dynamic with family package in the Xilinx System Generator (XSG), and realize with FPGA.

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